1. Field of the Invention
The present invention relates to flash memory devices, and more particularly, to a program control circuit for flash memory devices and a program control method performed using such program control circuits.
2. Description of the Related Art
In general, flash memory devices perform a read operation, a programming operation and an erase operation. The programming operation of the flash memory devices is performed through hot electron injection. The erase operation of the flash memory devices is performed through Fowler-Nordheim (FN) tunneling that occurs between a source electrode of a memory cell and a floating gate of the memory cell.
Flash memory devices perform these three operations as a result in changes in the magnitude of bias voltage(s) applied to a memory cell. In particular, during the programming operation of a conventional split-gate-type flash memory device, a program current flows between a source and drain of the memory cell that is being programmed. This is because the programming operation is performed by injecting a hot carrier generated from the source of the memory cell onto a floating gate of the memory cell. U.S. Pat. No. 6,014,331 discloses an exemplary circuit for programming a conventional split-gate-type flash memory cell and is hereby incorporated, in its entirety, by reference.
Conventional split-gate-type flash memories include memory cells arranged in an row-and-column array structure, as illustrated in FIG. 1 which provides a block diagram of a small portion of a conventional split-gate-type flash memory cell array. As illustrated in FIG. 1, memory cells C00–C02 share a word line WL0 and memory cells C10–C12 share a word line WL1 and all six memory cells C00–C02 and C10–C12 share a common source line SL0. Further, the memory cells C00 and C10 share a bit line BL0, the memory cells C01 and C11 share a bit line BL1, and the memory cells C02 and C12 share a bit line BL2.
FIG. 2 is a cross-sectional view of a conventional split-gate-type flash memory cell. As shown in FIG. 2, a split-gate-type flash memory cell 10 includes a substrate 11, a source 12, a drain 13, a floating gate 14, and a control gate 15. The programming operation of the split-gate-type flash memory cell 10 is performed by injecting hot carriers generated from the source 12 onto the floating gate 14 through a channel 17 and an insulating layer 16.
Hereinafter, a program control circuit of a flash memory device according to conventional art will be described with reference to FIG. 3. In memory cell C10 of FIG. 3, the gate is connected to a word line WL1, the drain is connected to a bit line BL0, and the source is connected to a source line SL0. The memory cell C10 also shares the source line SL0 and the bit line BL0 with a memory cell C00.
A program control circuit 20 is connected to the bit line BL0 that is, in turn, connected to the drain of the memory cell C10 that is to be programmed. The program control circuit 20 includes a first switching control portion 21, a first switching circuit N1, an inverter 22, a second switching control portion 23, a second switching circuit 24, and a current sink N3. When the memory cell C10 is programmed, the first switching circuit N1 and the second switching circuit 24 are turned on and different bias voltages are applied to the word line WL1, the bit line BL0, and the source line SL0. For example during a programming operation for memory cell C10, a high bias voltage of 4V may be applied to the word line WL1, a bias voltage of 0.8V may be applied to the bit line BL0, and a bias voltage of 4.5V may be applied to the source line SL0. Simultaneously, a voltage of 0V may be applied to word line WL0, which is connected to the gate of the memory cell C00 that is not being programmed. Also, although not indicated in FIG. 3, a high bias voltage, e.g., a bias voltage of 5V, may also be applied to the bit lines BL1 and BL2.
When the memory cell C10 is programmed, the bias voltage of 4V is applied to the word line WL1 and the memory cell C10 is turned on, allowing a program current Ip to flow between the source and drain of the memory cell C10. As the programming operation progresses, a threshold voltage of the gate of the memory cell C10 will tend to increase. As a result, the ability of the program current Ip to flow between the source (12 of FIG. 2) and drain (13 of FIG. 2) of the memory cell C10 using only the bias voltage (VG of FIG. 2) applied to the gate of the memory cell C10 will tend to be reduced or eliminated.
More specifically, the amount of time required to complete the programming operation will tend to vary with characteristics of memory cells to be programmed. As a result, a programming operation of specific duration may result in the over-programming of some memory cells. As a result of the over-programming, some of electrons injected during the programming operation may tend to remain in the floating gate (14 of FIG. 2) of a memory cell even after an erase operation has been completed.
This phenomenon is greatly affected by the number of programming operations performed on a memory cell and the characteristics of the particular memory cell. In other words, when the programming operation has a duration in excess of that required to fully program a particular memory cell, that the memory cell will tend to become over-programmed. Conversely, when the erase operation is of insufficient duration to remove the necessary number of electrons, some of electrons injected onto the floating gate of the memory cell during the programming operation may tend to remain in the floating gate of the memory cell.
For example, assuming that some of electrons are not discharged, but remain in the floating gate of the memory cell C10, when the memory cell C10 is programmed again, additional electrons are injected onto the floating gate of the memory cell C10 again. As a result, memory cell C10 will tend to contain more than the desired number of electrons in its the floating gate.
Further, during the programming operation, it is desirable to inject electrons onto the floating gate of the memory cell C10 in such a way that the flow of the program current Ip is generally maintained for the duration of the operation. However, when too many electrons are present in the floating gate of the memory cell C10, the program current Ip will tend to be reduced or interrupted. As a result, the desired program current Ip would no longer be supplied to the bit line BL0. As a result of this interruption, the first switching circuit N1 and the second switching circuit 24 are being turned on, the voltage level of the bit line BL0 becomes 0V through operation of the current sink N3.
As a result, punch through may occurs in memory cell C00 that shares bit line BL0 and source line SL0 with the memory cell C10 being programmed. As used herein, punch through indicates that current begins to flow between the source and drain of the memory cell C00 even when the memory cell C00 is turned off. Punch through occurs because the memory cell C00 that is not being programmed shares source line SL0 and bit line BL0 with the memory cell C10.
When the voltage level of the bit line BL0 connected to the drain of the memory cell C00 becomes 0V, a relatively high bias voltage (e.g., 4.5V) is applied to the source line SL0. As a result, although the memory cell C00 is not turned on, a current flows between the source and drain of the memory cell C00 due to the large voltage difference created between the source and drain. Such punch through tends to degrade the performance of a memory cell and shorten the operational life span of a memory cell.
Also, when the voltage level of the bit line BL0 becomes 0V, there is a high probability that the memory cell C10 is over programmed. This is because electrons are continuously injected onto the floating gate of the memory cell C10 from the source of the memory cell C10, even when the program current Ip is no longer supplied to the bit line BL0. Accordingly, it is necessary to control a variable voltage level of a bit line within a predetermined scope in a programming operation.